Generally, read-only memory (ROM) will include a high voltage programming pin (VPP) to induce channel hot electrons or to program memory cells. A device may, for instance, include a VPP which may accept a high voltage signal (e.g., 7 volts) for programming, and an ESD protection circuit to conduct large ESD current during, for example, an ESD event. Typically, from an ESD protection design point of view, the ESD protection circuit should have a small pad area, low power on rise time, and be latch-up free. In addition, from a time to market and cost point of view, the ESD protection circuit should be easily implemented for many process nodes, for example, by allowing for a one shot tape-out and requiring no mask revisions. As such, manufacturers face significant challenges for providing ESD protection circuits to address design, time to market, and cost criteria.
One commonly used ESD protection scheme uses a grounded-gate NMOS (ggNMOS). However, a ggNMOS has a large pad area (e.g., 50% of the ROM chip area), and often has a triggering voltage (e.g., 7 volts) close to a voltage of the VPP (e.g., 7 volts), which frequently causes a mistriggering of the ggNMOS resulting in a failure in functionality. Thus, an ESD protection scheme using a ggNMOS is generally unsuitable for ESD protection for circuits with a high voltage programming pad.
FIG. 1 schematically illustrates an RC clamp which is a first common solution for providing ESD protection for circuits with a high voltage programming pad. As shown, the circuit in FIG. 1 includes a VPP 101 connected to a power rail 103. Moreover, the power rail 103 is connected to a resistor 105, which in turn is connected to a ground rail 107 through a capacitor 109, and also to the gates of transistors 111 and 113. Additionally, the gate of a transistor 115 is connected to the drains of transistors 111 and 113. Resistor 105 and capacitor 109 are used to obtain a long RC time constant to turn on transistor 115. When turned on, transistor 115 creates a path 117 to conduct large ESD current during an ESD event, such as ESD zapping. However, the RC clamp ESD protection scheme in FIG. 1 requires a large pad area to implement the resistor 105, capacitor 109, and transistor 115, in order to gain a robust ESD performance. Additionally, circuits including a one-time programming (OTP) or multi-time programming (MTP) ROM cannot reduce the power up rise time due to a possibility of introducing false triggering during testing. Thus, the ESD protection scheme in FIG. 1 constrains testing time.
FIG. 2 schematically illustrates a common ESD protection circuit using a traditional LVTSCR. As shown, the circuit in FIG. 2 includes a low voltage (e.g., 8 volts to 8.5 volts) triggered silicon-controlled rectifier 201 (LVTSCR) having a first n-type layer with a cathode connection 203 connected to a ground rail, a first p-type layer, a second n-type layer with a control connection 205 connected to a trigger component 207, and a second p-type layer with an anode connection 209 connected to a power rail. The LVTSCR ESD protection requires only a small pad area. However, when this device is triggered, snapback will be induced and the operation voltage between VPP pad and ground will be clamped at a very low voltage, holding voltage Vh. A low Vh yields good ESD performance. However, during normal operation (e.g., an operating voltage of 1.8 volts, 3.3 volts, etc.), the holding voltage Vh will be less than the normal operating voltage, which, causes the LVTSCR to latch-up, resulting in a failure of chip function.
A need therefore exists for methodology enabling ESD protection for circuits with a high voltage programming pad that has a small pad area, low power on rise time, and is latch-up free.